1. Field of the Invention
The present invention relates to data processing systems, and more particularly to data processing systems including mechanisms for efficiently providing the functional capability of a host bridge while also providing dual (two) bus interfaces for a secondary bus, such as a Peripheral Component Interconnect (PCI) bus, or the like.
2. Description of Related Art
Many standard bus architectures for use in data processing systems such as the Peripheral Component Interconnect (PCI) bus specification contain ordering rules for transactions that traverse a bus to bus bridge, which connects at least two buses having the same bus protocol. Examples of such transactions are read requests outbound from a host processor to a peripheral device, read replies (responsive to the read requests) containing the data from the peripheral device inbound to the host processor or posted writes in which a write command is posted to a buffer in a bus to bus bridge allowing the host to proceed with other processing. A posted write herein means that the write has completed on the initiating bus and is posted in the host bridge for future completion on the destination bus. Current bus to bus bridge architectures either require write buffers in both outbound (away from the host processor) and inbound (towards the host processor) direction to be flushed out prior to completing a read transaction that traverses the bus to bus bridge, or define specific bus to bus ordering rules such as set forth in the PCI Local Bus Specification, version 2.1, for the PCI bus architecture. The requirement to flush the buffers can create a performance problem for a busy server by holding up the processor read accesses which are retried if there are any posted writes in the bridge buffers. Retry herein means that the target device being addressed by the master acknowledges the access but signals that it is busy and it terminates the transaction. The master then tries the access again at a later time.
Also current bus to bus bridge architectures usually provide one primary interface and one secondary interface. The PCI bus architecture results in limited bus loading capability of only ten (10) bus loads. One soldered device (adapter) counts as one load, and a slotted adapter counts as two loads. As a result, a PCI host bridge can have only a maximum of 4 slots directly attached to its secondary bus. If fewer slots are attached, then more soldered devices can be attached. The host bridge also counts as one of the 10 loads on the secondary bus. This results in a need within a system that requires many slots, to either provide multiple host bridges, or to provide multiple PCI--PCI bridges, or a combination of both to generate the needed slots.
A bus to bus bridge which connects one PCI bus to another PCI bus is herein referred to as a PCI--PCI bridge. Ordering rules for transactions that traverse a PCI--PCI bridge are included in the PCI local Bus Specification, revision 2.1. A bridge which connects a host processor(s), system bus or other system interconnection to a PCI bus is referred to herein as a PCI Host bridge (PHB), or host bridge.
Host Bridges have unique requirements above that required of PCI--PCI bridges, but also do not have all of the same constraints as a PCI--PCI bridge since for a host bridge, the source of most transactions on the primary (system) side of the host bridge interface are initiated by a host processor(s) rather than an I/O Device.
An article in the IBM Technical Disclosure Bulletin dated July, 1992, at page 233 and entitled "Architecture for High Performance Transparent Bridges," shows architecture for high performance bridges with multi-port bridges interconnecting networks including buffering components which guarantee transfer of data whether read or write with uniform handling inside the bridge.
Although the article generally relates to improvement in performance of bridges, the article does not address the problem of bus loading restrictions and ways to alleviate these restrictions.
U.S. Pat. No. 5,333,269 entitled "Mechanism for Transferring Messages Between Source and Destination Users Through a Shared Memory," teaches a common bus to which a memory with a number of independent buffers, a memory interface and a central control unit are connected. The memory interface receives messages from source users, stores the message in selected buffers, and chains the buffers together. The control apparatus generates inbound message cues and outbound message cues in response to commands which it receives from the memory interface.
Although the patent has some similarities to high performance bus bridge architectures, the patent does not address nor suggest a solution to the problem of limited bus loading capabilities.
U.S. Pat. No. 5,247,620 entitled "Bridge Apparatus with an Address Check Circuit for Interconnecting Networks," teaches multiple inbound and outbound buffers for reading out information from processor to peripheral devices and for bridging in a network environment.
Although the patent shows, in FIG. 1, a bus to bus bridge including a buffer memory, the patent does not teach nor suggest a mechanism for improving bus load capability in bus to bus bridges which eliminates the need for multiple host and/or multiple PCI--PCI bridges, or the like.
None of the prior art teaches nor suggests a method for reducing the requirement for including multiple bridges for addressing fan-out (load) capability.
In particular, a specific problem exists when a system requires more secondary bus slots than normally allowed (such as a maximum of four slots for a PCI bus), and requires efficient peer to peer operations. The current solution in the industry for this problem is to provide additional host bridges, or provide multiple PCI--PCI bridges to generate the added slot capability beyond the typical four slot capacity of one host bridge. These conventional techniques attempt to solve the requirement of additional slots, but they do not address the need for efficient peer to peer support while minimizing the number of host and bus to bus bridges.